1. Field of the Invention
The present invention relates to a semiconductor memory device and, for example, a semiconductor memory device having static memory cells.
2. Description of the Related Art
A static random access memory (SRAM) is known as a kind of semiconductor memory device. The SRAM uses, as a memory cell, an SRAM cell (six-transistor SRAM cell) including, e.g., six metal oxide semiconductor (MOS) transistors.
The six-transistor SRAM cell comprises two inverter circuits. The output terminal of one inverter circuit is connected to the input terminal of the other inverter circuit. The six-transistor SRAM cell also has two transfer gates which connect the two data storage nodes of the SRAM cell to bit lines in the data read and write modes. The transfer gates are connected to a word line which turns the transfer gates on or off.
A row decoder to select word lines and a word line driver to drive the word lines on the basis of the decode signal of the row decoder are connected to the word lines. For example, a variable power supply voltage VDD of about 0 to 1.2 V is applied to the row decoder, and a fixed power supply voltage VDDA of about 1.2 V is applied to the word line driver. The power consumption can be reduced by dynamically changing the variable power supply voltage VDD in accordance with the operation mode of the chip.
The SRAM cell cannot greatly decrease the power supply voltage because of the need for ensuring the data hold stability. The word line potential cannot greatly be decreased, either, from the viewpoint of ensuring a write margin and ensuring a cell current. For these reasons, the fixed power supply voltage VDDA of about 1.2 V is applied to the SRAM cells and word line driver in an SRAM of, e.g., 65-nm generation.
As described above, the variable power supply voltage VDD is applied to the row decoder. Hence, the decode signal of the row decoder swings within the range of about 0 to 1.2 V. When the decode signal is high (i.e., when a word line is selected), and the variable power supply voltage VDD is 1.2 V or less, the high-level voltage of the decode signal also drops to 1.2 V or less. Since the P-channel MOS transistor of the first-stage inverter circuit included in the word line driver that receives the decode signal cannot be completely turned off, the through current flowing to the first-stage inverter circuit increases. This increases the leakage current of the word line driver.
An associated technique of this type is disclosed, which reduces power consumption by providing a switch in a peripheral circuit of a memory cell array and causing the switch to cut off a fixed power supply (Jpn. Pat. Appln. KOKAI Publication No. 11-219598).